Methods for power minimisation in modern VLSI circuits

Power Minimisation Techniques for Testing Low Power VLSI Circuits

A Minimal-Cost Inherent-Feedback Approach for Low-Power MRF-Based Logic Gates

The Markov random field (MRF) theory has been accepted as a highly effective framework for designing noise-tolerant nanometer digital VLSI circuits. In MRF-based design, proper feedback lines are used to control noise and keep the circuits in their valid states. However, this methodology has encountered two major problems that have limited the application of highly noise immune MRF-based circui...

Spice Compatible Model for Multiple Coupled Nonuniform Transmission Lines Application in Transient Analysis of VLSI Circuits

An SPICE compatible model for multiple coupled nonuniform lossless transmission lines (TL's) is presented. The method of the modeling is based on the steplines approximation of the nonuniform TLs and quasi-TEM assumptions. Using steplines approximation the system of coupled nonuniform TLs is subdivided into arbitrary large number of coupled uniform lines (steplines) with different characteristi...

Test Power Reduction by Simultaneous Don’t Care Filling and Ordering of Test Patterns Considering Pattern Dependency

Estimating and minimizing the maximum power dissipation during testing is an important task in VLSI circuit realization since the power value affects the reliability of the circuits. Therefore during testing a methodology should be adopted to minimize power consumption. Test patterns generated with –D 1 option of ATALANTA contains don’t care bits (x bits). By suitable filling of don’t cares can...

High Performance VLSI Design Using Body Biasing in Domino Logic Circuits

Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. The main drawbacks of dynamic logic are a lack of design automation, a decreased tolerance to noise and increased power Consumption. Dynamic CMOS circuits, featuring a high spee...